1. Field of the Invention
The present invention relates to a technique for surely detecting a failure of a memory cell of a semiconductor memory.
2. Description of the Related Art
A memory cell array of a semiconductor memory includes a plurality of memory cells arranged in a matrix and wirings (word lines and bit lines) for connecting those memory cells to a word decoder, a sense amplifier, and the like. In the memory cell array, elements and wirings are arranged with higher density, as compared with those in circuits near the memory cell array. In other words, the layout density of the elements and wirings on the inside of the memory cell array is different from that on the outside thereof. Thus, the shapes of the elements and wirings in an inner region of the memory cell array may be different from those in an outer peripheral region because of halation or the like in a fabrication process. Such a difference of the shapes may cause a short failure and a disconnection failure, thus reducing a yield.
According to a conventional technique, in order to make the shapes of the elements and wirings in the inner region of the memory cell array the same as those in the outer peripheral region so as to increase the yield, dummy memory cells and a dummy wiring (such as a dummy word line) are formed in the outer peripheral region of the memory cell array. Onto the dummy memory cell, no data has to be written (i.e., the dummy cell is not accessed), as described in Japanese Unexamined Patent Application Publications Nos. 2000-207899 and 2001-351399, for example. Therefore, the dummy memory cell is formed to have a simpler structure than that of a memory cell onto which given data is written (i.e., real memory cell).